Clocks & timing

The CDCBT1001 is a 1.2-V to 1.8-V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2 V ± 10%. VDD_OUT = 1.8 V ± 10% The 12-kHz to 5-MHz additive RMS jitter at 24 MHz is less than 0.8 ps.

The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations. On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode. Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply. The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.

The LMK5B33216 is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of ethernet-based networking applications with < 5-ns timing accuracy (class D). The network synchronizer integrates three DPLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a reference input. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology and can generate 312.5 MHz output clocks with 42-fs typical / 60-fs maximum RMS jitter irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 provide options for a second or third frequency and/or synchronization domain. Reference validation circuitry monitors the DPLL reference clocks and performs a hitless switch between them upon detecting a switchover event. Zero delay and phase buildout may be enabled to control the phase relationship from input to outputs. The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

Texas Instruments’ Bulk-Acoustic Wave (BAW) is a micro-resonator technology that enables the integration of high-precision and ultra-low jitter clocks directly into packages that contain other circuits. BAW is fully designed and manufactured at TI factories like other silicon-based fabrication processes. The LMK6x device is a low jitter, fixed-frequency oscillator which incorporates the BAW as the resonator source. With a high-performance fractional frequency divider, the LMK6x is capable of producing any frequency within the specified range providing a single device family for all frequency needs. The device is factory-programmed per specific operation mode, including frequency, voltage, output type, and function pin. Contact a TI representative for additional frequencies or other options. The high-performance clocking, mechanical stability, flexibility and small package options for this device are designed for reference and core clocks in high-speed SERDES used in Telecommunications, Data and Enterprise Network and Industrial applications.

The TPL5110-Q1 Nano Timer is a low power, AEC-Q100 qualified timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110-Q1 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110-Q1 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110-Q1 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110-Q1 is available in a 6-pin SOT23 package.

The LMX2571-EP device is a low-power, high-performance, wideband PLLatinum™ RF synthesizer that integrates a delta-sigma fractional N PLL, multiple core voltage-controlled oscillator (VCO), programmable output dividers and two output buffers. The VCO cores work up to 5.376 GHz resulting in continuous output frequency range of 10 MHz to 1344 MHz. This synthesizer can also be used with an external VCO. To that end, a dedicated 5-V charge pump and an output divider are available for this configuration. A unique programmable multiplier is also incorporated to help improve spurs, allowing the system to use every channel even if it falls on an integer boundary. The output has an integrated SPDT switch that can be used as a transmit and receive switch in FDD radio application. Both outputs can also be turned on to provide 2 outputs at the same time. The LMX2571-EP supports direct digital FSK modulation through programming or pins. Discrete level FSK, pulse shaping FSK, and analog FM modulation are supported. A new FastLock technique can be used allowing the user to step from one frequency to the next in less than 1.5 ms even when an external VCO is used with a narrow band loop filter.