Logic & voltage translation

This device contains eight independent inverting line drivers with 3-state outputs and Schmitt-trigger inputs. Each channel performs the Boolean function Y = A in positive logic. The channels are grouped in sets of four, with one OE pin controlling each set. The outputs can be put into a hi-Z state by applying a high on the associated OE pin.

The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation. This device consists of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 shows the four fundamental bus-management functions that are performed with the SN54LVC646A device. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver

The SN74HCS574-Q1 contains eight D-type flip-flops. All inputs include Schmitt-trigger architecture. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.

The ’HC4060-Q1 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the clock (CLKI) input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO goes high and CLKO goes low) and resets the counter to zero (all Q outputs low).

This device contains four independent 2-input XNOR gates with open-drain outputs and Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ⊕ B in positive logic.

This device contains four independent 2-input AND gates with open-drain outputs and Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B in positive logic.

The SN74HCS251 is a data selector/multiplexer containing full binary decoding to select 1-of-8 data sources and features strobe-controlled complementary 3-state outputs.

CD40117B is a dual 4-bit terminator that can be programmed by means of STROBE and DATA control bits to function as pull-up or pull-down resistors. The CD40117B can also be programmed to function as latches to terminate any open or unused CMOS logic when used with 3-state logic or during a power-down condition. Considerable savings in power and board space can be realized when this device is used to replace pull-up or pull-down resistors. When the STROBE is in the logic “”1″” state, the terminator functions as a pull-up resistor if the DATA input is a logic “”1″” or as a pull down resistor if the DATA input is a logic “”0″”. When the STROBE is in the logic “”0″” state, the terminator performs the latch functions, i.e., it follows the changing states of the bus. If the bus goes into the high-Z state or into a power-down condition, the latched terminator retains the data (“”1″” or “”0″”) that the bus carried before it switched to the high-Z or power-down state. If and when the bus changes from the high-Z state to the state opposite to that which the latch is storing, the bus will override the latch and the terminator will reflect the state on the bus. The small geometries chosen for the inverters in the latch allow this override mode. When checking the data bus whose last state is being preserved by the terminator, a resistor should be used in series with the probe whose input capacitance could trip the small latches. The resistance should be in excess of the output impedance of the latch, i.e., R should be > 30 K at VDD = 10 V. The STROBE and DATA inputs in each section can be paralleled allowing this device to be used as an 8-bit bus terminator. The CD40117B types are supplied in 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

The SN74LV4T125-Q1 contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The TXS0206A is a level shifter for interfacing microprocessors with MultiMediaCards (MMCs), secure digital (SD) cards, and Memory Stick™ cards. The voltage-level translator has two supply voltage pins. VCCA as well as VCCB can be operated over the full range of 1.1 V to 3.6 V. The TXS0206A enables system designers to easily interface applications processors or digital basebands to memory cards and SDIO peripherals operating at a different I/O voltage level. The TXS0206A is offered in a 20-bump wafer chip scale package (WCSP). This package has dimensions of 1.96 mm × 1.56 mm, with a 0.4-mm ball pitch for effective board-space savings. Memory cards are widely used in mobile phones, PDAs, digital cameras, personal media players, camcorders, set-top boxes, etc. Low static power consumption and small package size make the TXS0206A an ideal choice for these applications.